Embodiments of the inventive concept described herein relate to semiconductor memory devices, and more particularly, program verifying methods of nonvolatile semiconductor memory devices.
Semiconductor memories include volatile memories, such as dynamic random access memory (RAM) (DRAM), static RAM (SRAM), and the like, and nonvolatile memories, such as electrically erasable programmable read-only memory (EEPROM), ferroelectric RAM (FRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), resistive random-access memory (ReRAM), flash memory, and the like. The volatile memories lose data stored therein at power-off, while the nonvolatile memories retain data stored therein even at power-off. The flash memory in particular has merits such as a high read speed, low power consumption, storage of a large amount of data, and the like. Thus, data storage devices including flash memory are widely used as storage mediums.
As nonvolatile memory, a floating gate type flash memory stores bit information by injecting charges in a floating gate formed of polysilicon. In the flash memory, a memory cell may be used as a single level cell (SLC) storing one of two states “1” and “0”, or as a multi-level cell (MLC) storing one of four states “11”, “01”, “10” and “00”.
A Charge Trap Flash (CTF) memory is used to solve problems due to capacitive coupling between conductive floating gates, and uses a memory layer (i.e., a charge storage layer) instead of a conventional conductive floating gate. Threshold voltage distributions of programmed memory cells in a CRF memory are rearranged in charge storage layers during a program verify operation for verifying programming of memory cells. This may mean that threshold voltage distributions are varied. Thus, it is difficult to perform a program verify operation exactly using a conventional method where a read voltage is decided by setting constant margins at left and right sides of a threshold voltage distribution of multi-level cells. As a result, errors may occur.